The present invention relates to the field of semiconductor integrated circuits and, in particular, to capacitor arrays formed over the bit line of an integrated circuit substrate.
The current semiconductor industry has an ever-increasing pressure for achieving higher device density within a given die area. This is particularly true in memory circuit fabrication, for example Dynamic Random Access Memory (DRAM) manufacturing. A memory cell of a typical DRAM includes a storage capacitor and a charge transfer field effect transistor. The binary data is stored as electrical charge on the storage capacitor in the individual memory cell.
In the early days of DRAM development, planar-type storage capacitors were used which occupied large substrate areas. These were later replaced with container capacitors which occupied less surface area. Recently, however, with the number of memory cells on the DRAM chip dramatically increasing, the miniaturization of DRAM devices requires smaller capacitor features as well as increased storage capacitance.
Different approaches have been employed to achieve higher storage capacitance on a given die area to meet the demands of increasing packing density. For example, with trench capacitors, electrical charge has been stored in capacitors formed vertically in a trench that requires a deep trench formation, but this encounters significant processing difficulties. Another approach is to build a stacked container storage capacitor over at least a portion of the transistor to allow, therefore, smaller cells to be built without losing storage capacity. Stacked capacitors have become increasingly accepted in the semiconductor art. However, as the device density continues to increase, the planar surface area required for building the conventional stacked capacitors must be further reduced. Further, the topography of currently fabricated devices requires more difficult planarization processes to be performed on the DRAM devices.
Accordingly, there is a need for an improved method for fabricating stacked capacitors that minimizes the drawbacks of the prior art. There is also a need for stacked capacitors which have minimal spacing that is not afforded by current photolithographic feature sizes.
The present invention provides a method for forming stacked capacitors in high density, in which a plurality of patterned capacitor outlines in the form of walls, are formed over the bit line of a semiconductor device. In one aspect of the invention, spacers are formed on the patterned capacitor walls and become part of the cell polysilicon after being covered with cell nitride. In another aspect, the spacers are formed of a material capable of being etched back, such as titanium nitride. In another aspect, a metal layer is patterned and annealed to a polysilicon layer to form a mask for a capacitor array, and subsequently etched to form the array.
Additional features and advantages of the present invention will be more clearly apparent from the detailed description which is provided in connection with accompanying drawings which illustrate exemplary embodiments of the invention.